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quartus ii中实现开漏极输出

2008-12-26 17:24 3089 0 1 分类: FPGA/CPLD
http://www.altera.com/support/kdb/solutions/rd06252007_878.html

设置上拉,驱动电流等方法都在altera的http://www.altera.com.cn/support/devices/io/features/io-features.html


Problem


How do I implement open drain outputs in the Quartus II software?



Solution

You can implement an open drain output signal using standard
VHDL or Verilog HDL statements, or by instantiating an Altera? open
drain (OPNDRN) primitive.


Method 1. Use one of the following HDL statements to create an open drain output for a signal called top_out:


VHDL:  top_out <= 'Z';
Verilog HDL:  assign top_out = 1'bZ;


Method 2. Use the Altera OPNDRN primitive to create an open drain
output. This primitive is defined in Quartus? II Help as described
below.


VHDL:
<instance_name>: opndrn PORT MAP (
a_in => <input_wire>,
a_out => <output_pin>
);


The VHDL component is declared in an Altera primitives library. Use the following commands to include the library:


LIBRARY altera;
USE altera.altera_primitives_components.all;


Verilog HDL:
OPNDRN <instance_name> (.in(<input_wire>), .out(<output_pin>));



You can use the Quartus II language templates to help you
instantiate the primitive. Right-click in the Quartus II text editor
and choose Insert Template. In the Language templates list, expand the list for VHDL or Verilog HDL, then expand Altera Primitives, and then Buffers. Choose the OPNDRN primitive and click Insert. You can then customize the instantiation and continue design entry.


To confirm that the open drain output pin was implemented, check the Compilation Report. In the Fitter section of the report, expand the Resource Section and click Output Pins. The Open Drain column indicates yes for any open drain output pins.

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495065379_992161927 2014-1-13 14:58

有没有TCL 的设置方法 类似于 set_location_assignment
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