广告

XILINX DDR 控制器约束问题的解决

2010-7-14 20:01 3382 0 分类: FPGA/CPLD

http://www.zdh1909.com/html/fpga/9599.html


该文章讲述了XILINX DDR 控制器约束问题的解决.

我的项目在添加MIG3.2的约束文件后,会出现一些错误,这些错误大都会指出未知道指定的网点名字,打开约束文件分析是约束文件的路径和本项目路径不一致,在前面加例化模块名如U_DDR_ctrl解决了一些错误,但还会出现一些错误,如下:

ERROR:ConstraintSystem:58 - Constraint <NET

   "U_DDR_ctrl/top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk" TNM_NET = "fifo_we_clk";> [VIDEO_SYNTH.ucf(2)]: NET

   "U_DDR_ctrl/top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_ins

   t/clk" does not match any design objects.

这个错误是最前面的约束错误,也意思是找不到匹配的对象。检查路径没有错误,把该约束内容删除,打开空白时序约束编辑器,进行TNM_NET约束,查找网点,未找到CLK的信号,连CLK例化信号dqs_delayed_col1_n、dqs_delayed_col0也没找到,而发现在它的上一级模块中,如果对她们进行约束不能串过前一级还不能对指定的路径进行约束,寻求改信号名或更改路径方法约束较麻烦,就暂时放下。经过网络搜索也没有找到解决办法。这个问题困绕着两天没有解决。突然想起直接把前述的错误提示NET "top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk"输入GOOGLE搜索(GOOGLE在搜索这方面还是很强大的,百度就不行了,题外话,呵呵),终于找到问题解决方法了。原来要设置综合属性保持模块层次设置为soft,该设置意思是综合保持层次结构属性,但布局布线就不保持。还有YES和NO,自然明白其意义了,就不说了,缺省为NO。这样,问题迎刃而解,所有的约束都能修改好。


http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-3E-DDR-MIG/m-p/32967/page/2


Hi,

 

The two possible causes of your "problem", at least as far as I can figure out, are:

 

- Different naming in the structure. You need to modify the U_4/etc... in the .ucf stuff to match the names of the instance as you have actually named them in your code, structural one. Indeed I had to do it by hand from the MIG generated UCF; if I did not do so I got the same kind of messages.

- Beware of the synthesis options. Chances are that you do not have kept the "Keep hierarchy" setting, and the synthesizer is throwing those signal names away. This is very needed for the DDR controller itself; in my project I set to "Soft" and it works. Whenever I set "No" to keep the hierarchy, I had the same messages as you are having.

 

Good luck!


Hi Sanjaac,

 

thanks for your reply...with attribute "soft" now the design compile!!!!

 

I test the first task "the ddr initialization" and everything goes well.

 

Now I would write some data, but I do't understand well the timing diagram on UG086 page 254 figure 7-9 (see the attach)

 

my first question : what is D0,D1, Dx..? is D0 a word of 4 byte?So every burst I'll write 32 bytes of data?

 



广告

文章评论 0条评论)

登录后参与讨论
相关推荐阅读
shangdw 2010-12-22 10:59
microblaze lmb bram
entity lmb_v10 is generic ( C_LMB_NUM_SLAVES : integer := 4; C_LMB_DWIDTH : integer :...
shangdw 2010-12-22 08:55
microblaze SDRAM
BEGIN mpmc PARAMETER INSTANCE = mpmc_0 PARAMETER HW_VER = 5.00.a PARAMETER C_MEM_PARTNO = MT48LC32M1...
shangdw 2010-08-16 16:18
自己归纳整理的ARM THUMB指令机器码表
http://download.ednchina.com/Detail/121141/资料名称:自己归纳整理的ARM THUMB指令机器码表整理日期:2010/4/23详细介绍:        有个项...
shangdw 2010-08-03 19:30
FPGA logic analyzer
http://www.saleae.com/logic/etail. Lots of it.Store up to 500M samples at speeds as fast as 24MB/s.U...
shangdw 2010-07-21 16:06
跟我写ARM处理器之一:从写module arm( 开始
http://free-arm.blog.163.com/blog/static/1076779632009497742348/跟我写ARM处理器之一:从写module arm( 开始  我决定把我写...
shangdw 2010-07-17 22:39
FPGA Based Logic Analyzer
FPGA Based Logic AnalyzerThe outcome of this project is a logic analysator for home use.The project ...
我要评论
0
0
广告