Guard very high-speed data lines by taking into account the capacitance and placement of ESD suppression devices.
Circuit designers face many electrostatic-discharge (ESD) concerns in their quest for a functional and reliable product. Moreover, the evolution of the electronics marketplace toward higher data throughput and faster signal speeds adds to this complexity. Basically, ESD protection falls into two categories: protection during manufacturing, and protection in the "real-world" environment.
On-chip transient-voltage-suppression (TVS) structures are designed to increase chip yields in foundry and board-manufacturing environments. They typically follow such standards as the Charged Device Model (CDM), the Machine Model (MM), and the Human Body Model, MIL-STD HBM. But the severity of ESD in the "real-world" environment is much higher.
Everyday users of electronic products (cell phones, PDAs, laptop computers, etc.) introduce a more severe level of ESD into those products. These ESD transients are typified in the IEC 61000-4-2 test methodology. It's important to remember that survival through the manufacturing process does not guarantee survival in the hands of the end-user. "Supplemental" ESD protection, like ESD suppressors, may be necessary. This article focuses on critical selection criteria of ESD suppressors and provides recommendations and supporting data for guiding optimal ESD protection at the board level.
Designers need to understand not only the suppression characteristics of ESD protectors, but also their package characteristics. It's extremely important that stray characteristics, such as capacitance, are understood in order to take them into consideration during the board design. In other words, make sure the ESD suppressor is a good fit with the circuit parameters (data rates, leakage current, and so on).
Optimal placement of ESD suppressors begins at the location of ESD penetration into the system. This tactic reduces the ESD voltage and current initially experienced by the circuit and attenuates the ESD pulse that propagates past the ESD suppressor. Design as much practical space as possible between the ESD suppressor and the protected chip.
Placing an ESD suppressor too far away from the line it's protecting can reduce its effectiveness. The board trace inductance can cause an additional amount of voltage, or "overshoot," on the chip. To avoid this, install the ESD suppressor as close to the protected line as possible. The bottom line is that selecting an ESD "solution" is no longer as simple as choosing a suppressor that's rated for the operating voltage of the circuit. An effective solution now takes into account the layout of the circuit board, as well as the nonsuppression electrical characteristics of the ESD suppression devices. Before delving further into the specifics of ESD protection, it's helpful to review some fundamentals.
ESD basics: A topic of particular concern to designers is the inadvertent damage done by the end users of electronic products. Normal day-to-day activities can cause people to build up static electricity, which might later be transferred to objects like file cabinets, doors, and electronic devices. As a person walks across a carpeted floor, a transfer of charge occurs. Similarly, the act of sliding out of an office chair can cause a transfer between the chair and its occupant. This effect, called triboelectric charging, happens any time two dissimilar materials come into contact and then separate. The subsequent transfer of electrical charge to an object at lower electrical potential is referred to as electrostatic discharge.
The issue at hand for the design, quality, and reliability communities is the effect of static electricity transference on their electronic products. If the ESD pulse finds its way into the electronic devices, the circuitry inside can be physically damaged. The ESD Association has estimated the average loss of products due to user-generated ESD at 27% to 33%. Whether the product loss occurs at the user level or during the manufacturing process, ESD can lower product reliability and company profit. To help reduce losses due to ESD, chip manufacturers can incorporate TVS structures into their integrated circuitry dies. This will make them more robust and help to increase yields in chip-foundry and board-manufacturing processes.
The big problem occurs when the electronic product transfers from the manufacturing environment to actual daily use. The level of ESD the end user can generate and introduce to the electronic device is much more severe than the level found in the controlled manufacturing environment. This means that a design that had high yields during manufacturing can experience higher losses in the field. Consequently, the focus of ESD protection has shifted from chip hardening to system hardening.
ESD suppression: The ability of an IC or ASIC to survive the manufacturing process doesn't guarantee that it will survive "real world" usage. What can be done to improve the survivability, or reliability, of your design? Currently, numerous protection options are available to the designer. These in-clude isolation circuits, filtering circuits, and suppression components, such as multilayer varistors, silicon diodes, and the newly introduced polymer-based suppressors.
Suppression components protect the circuit by clamping the ESD voltage to a level that the circuit can survive. Connected in parallel with the signal lines, the suppressors clamp the ESD voltage and shunt the majority of the ESD current away from the data line, and the protected chip, to the appropriate reference. Typical references are the power rail and chassis ground.
While these approaches can all en-hance an electronic device's ESD survivability, there are inherent characteristics to consider during the selection process. Obvious characteristics include size, pin out, pad layout, and leakage current. But as the need for circuits to provide higher informational throughput increases, another characteristic becomes very important—capacitance.
Capacitance and signal integrity: Today and in the past, the inherent package capacitance of a suppressor could be used to the circuit designer's advantage. Where a high degree of separation exists between the signal frequency and any unwanted frequencies, like EMI "noise" and ESD transients, capacitance supplies the additional benefit of filtering. Essentially acting like a low-pass filter, the suppressor provides clamping functions for transient suppression and can provide EMI filtering against unwanted, high-frequency signals that couple into the protected data line.
For example, the headset terminals on a cell phone operate at relatively low frequencies (audio range), while ESD and the cell-phone operating frequencies (900 to 1900 MHz) are much higher. Here, high-capacitance multilayer varistors and diodes are ideal for ESD protection from the user. They have the additional benefit of filtering radiated cell-phone signals out of the headset lines.
This "benefit," however, becomes a detractor when the signal speed is increased. The need for higher informational throughput (video, audio, data) requires an increase in transmitted data rates. Examples of these "high-speed" data lines include the USB 2.0, IEEE 1394, Gigabit Ethernet, and InfiniBand protocols. Data rates of these protocols all exceed 100 Mbits/s.
At these speeds, the capacitance that helped to eliminate unwanted noise will also begin filtering the data signals themselves, resulting in distorted data waveforms that can render a system inoperable. The distortion takes the form of rounded leading and trailing edges of high/low state transitions due to slower rise and fall times.
Slower rise/fall times introduce problems into the circuit. Most importantly, timing issues can come up. The circuit expects "high" and "low" states to be stable at specific times. As the transition time between states increases, the circuit can be caught sensing an incomplete transition, and data errors can be introduced into the system.
Circuits will operate as they were designed as long as the information controlling them conforms to the intended protocol. When components of the signals degrade, the circuit's ability to recognize the intended information decreases. From a circuit-protection standpoint, the goal is to provide ESD protection to the circuit and to maintain the integrity of the data, not to interfere with circuit operation.
To investigate the effect that package capacitance has on data integrity, results were collected at two data frequencies. The specific technologies used aren't the focus here. Rather, the capacitance values are the important factors. The products used in the test were:
The PGB0010603 PulseGuard suppressor of 0.050 pF
An ML ceramic capacitor of 1.0 pF
An ML ceramic capacitor of 10.0 pF
The V5.5MLA0603 multilayer varistor of 660 pF
While the rise time (10/90%) of the 12-Mbit/s waveform of Figure 1 is fast (0.242 ns), the time that it holds its level is considerably longer (80 ns). At this data rate, a capacitance value of 10 pF or less will allow the data to pass with minimal distortion. But the 660-pF capacitance value clearly demonstrates how the leading and trailing edges of the data are rounded.
Contrast this information with Figure 2. Here, the same devices were tested with a data waveform of 480 Mbits/s. The rise time for the two signals is the same (0.242 ns), but the 480-Mbit/s signal has a much shorter level time of 2.0 ns. Note the different time scales of the two charts.
In this case, the 660 pF of capacitance causes so much distortion that the waveform isn't even able to reach the signal operating voltage. In essence, none of the data is propagated down the signal line. Even the capacitance value of 10 pF is high enough to cause substantial distortion to the waveform. It decreases the amount of level time and significantly changes the leading and trailing edge shapes. The capacitance value of 1.0 pF shows a small amount of edge distortion, while the 0.050-pF capacitance value allows the data waveform to pass without distortion. The table shows the rise time (10/90%) of the waveforms in Figure 2 (bit rate of 480 Mbits/s) for each capacitance value.
This data reveals how important the capacitance characteristic of an ESD suppressor is when protecting the data lines of very high-speed systems. While all existing suppressors can provide effective ESD protection, the signal integrity of the system can't be compromised. Therefore, the capacitance of an ESD suppressor must be considered before adding it to the circuit design. Extremely low-capacitance ESD-suppression components, such as the PulseGuard devices, can provide ESD protection functionality and still maintain the data integrity of high-speed data signals.
Installation considerations: After selecting an ESD suppressor whose suppression and electrical characteristics (leakage current, capacitance) are a good match for the circuit parameters, another choice remains: Where on the board should the suppressor be in-stalled to optimize the ESD protection for the circuit? "Optimized" ESD protection means that the protected chip sees as little of the ESD transient as possible.
High-speed signals and transients (like ESD) bring another parasitic characteristic into play—inductance. Of specific interest is the parasitic inductance of the board traces that are used as interconnects between the connector, the chip, and any support components. Similar to the capacitance effects, the inductance presented by board traces won't affect low-frequency signals. At high speeds, however, the inductance will present an impedance component that can affect signal integrity. Recall the formula for inductive reactance: XL = ωL. This can also be written as: XL = 2πfL.
A small amount of trace inductance can translate into a substantial amount of impedance when a high-frequency signal like ESD is run through it. Designers can take advantage of this by putting as much distance as possible between the ESD suppressor and the protected chip. Refer to Figure 3, where the following inductance values are represented:
L1—between the connector and the ESD suppressor
L2—between the ESD suppressor and the I/O pin of the chip
L3—between the I/O line and the ESD suppressor (stub trace)
In essence, the inductance attributable to L2 will dissipate the energy of the ESD pulse that remains after the clamping action of the ESD suppressor. Attenuation of the ESD pulse's voltage and current take place as the energy is stored and dissipated in the electromagnetic field around the board trace. Note that there's an inverse relationship between the length of board trace and ESD pulse energy that finally arrives at the chip's I/O pin. As the length of the trace increases, the strength of the ESD pulse (seen at the chip) decreases. The decreased ESD pulse translates into reduced stress on the chip.
The plots in Figure 4 show the voltage-versus-time values measured at two locations on a test board. They help us to understand the effects of where the ESD suppression device is placed. In this example, the suppressor was installed at the connector, the entry point for ESD transients.
The blue waveform shows the voltage measured on the I/O line, at the location of the ESD suppressor. The suppressor has responded to the 1000-V transmission-line pulser's pulse with a measured peak voltage of approximately 350 V and a "clamping," or holding, voltage of about 75 V.
Compare this to the green waveform, which shows the ESD pulse that actually gets to the IC. In this case, a 3-in. long trace (L2) connected the ESD suppressor site and the input pad for the IC. Note that the measured peak voltage has been reduced to 60 V and the "clamping" voltage is about 25 V.
What does this mean? For the circuit designer, this provides a tactic for minimizing the amount of ESD experienced on the I/O inputs of the ICs and ASICs. Increasing the amount of trace length between the ESD suppressor and the chip can dramatically reduce how much stress the IC experiences. Referring to Figure 3, this means that making the trace longer will increase the L2 value.
Plainly speaking, the ESD suppressor should be located directly behind the connector. It should be the first board-level component that the ESD transient encounters. Then, to the extent that it's practical, any chip to be protected should be located as far away as possible. As demonstrated in Figure 4, this tactic will drastically reduce the stress that the integrated circuitry experiences. The following list is arranged to show the relative preference of ESD suppressor installation locations. The optimal location is listed first, and the least preferred site is listed last:
Inside connectors that are the gateway in the system shielding (chassis)
At the point where circuit-board traces interact with the pins of the connector
On the circuit board immediately behind the connector
On robust, unprotected lines that may efficiently couple to I/O lines
Before a series resistive element on a data line
Before a fan-out point on a data line
Near the IC and/or ASIC
Another placement concern is the distance from the board trace to the ESD suppressor (L3 in Figure 3). The goal is to minimize this distance. The inductance associated with the trace, and any parasitic package inductance, will insert impedance in the protection circuit.
In essence, the ESD suppressor be-comes more "isolated" from the signal line that it's protecting as its distance from the line increases. Remember that the chip will experience the ESD voltage across the suppressor plus the voltage across the trace impedance. The ideal solder-pad placement would be right on top of the data line. If this isn't possible, then this distance should be minimized.
Finally, the chassis (frame) ground should be the ESD reference, not the signal (digital) ground (Fig. 3, again). The objective is to transfer the ESD out of the signal environment. By referencing the ESD TVS protection device to chassis ground, unintentional noise effects, like ground bounce, can be avoided. The goal is to keep the signal (data) environment as clean as possible.