tag 标签: ASML

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  • 热度 2
    2018-8-3 19:33
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    ASML出货5nm工艺的DUV光刻机,细说先进节点光刻技术及代工博弈 ... ... ...
    据外媒报道,光刻机霸主ASML(阿斯麦)已经开始出货新品Twinscan NXT:2000i DUV(NXT:2000i双工件台深紫外光刻机),可用于7nm和5nm节点。NXT:2000i将是NXE:3400B EUV光刻机的有效补充,毕竟台积电/GF的第一代7nm都是基于DUV工艺。 同时,NXT:2000i也成为了ASML旗下套刻精度(overlay)最高的产品,达到了和3400B一样的1.9nm(5nm要求执照2.4nm,7nm要求至少3.5nm)。 ASML将于本季度末开始量产Twinscan NXT:2000i,价格未披露。目前,NXE:3400B EUV光刻机的报价是1.2亿美元一台,传统的ArF沉浸式光刻机(14nm节点)报价是7200万美元之间, NXT:2000i肯定是在这两者之间了。 目前主流的半导体生产中使用的是波长193nm的深紫外(DUV)光刻。实际上,在制程发展到130nm之前,人们就曾指出193nm深紫外光会发生严重的衍射现象而无法继续使用,需要换用波长为13.5nm的极紫外(EUV)光刻才能继续缩小半导体工艺。此外,还有一些公司推崇的e-beam电子束光刻技术。 EUV的研发始于20世纪90年代,最早希望在90nm制程节点投入应用,然而EUV光刻机一直达不到正式生产的要求。无奈之下,人们只能通过沉浸式光刻、多重曝光等手段,将DUV一路推进到了10nm阶段。 ASML的EUV光刻机使用40对蔡司镜面构成光路,每个镜面的反光率为70%。这也就是说,EUV光束通过该系统中的每一对镜面时都会减半,在经过40对镜面反射后,只有不到2%的光线能投射到晶元上。 到达晶圆的光线越少,光刻所需的曝光时间就越长,相应的生产成本也就越高。为了抵消镜面反射过程中的光能损耗,EUV光源发出的光束必须足够强,这样才能与现在非常成熟的DUV光刻技术比拼时间成本。 但是多年以来,光照亮度的提升始终未能达到人们的预期,ASML的EUV产品市场负责人Hans Meiling曾表示,人们严重低估了EUV的难度。正在实验中的EUV光源焦点功率刚刚达到250瓦,可以支撑机器每小时处理125个晶片,效率仅有现今DUV的一半。 如果再加上价格和能耗,EUV取代DUV还会更加艰难。最新的EUV光刻机价格超过1亿欧元,是DUV光刻机价格的二倍有余,且使用EUV光刻机进行批量生产时会消耗1.5兆瓦的电力,远超现有的DUV光刻机。 ASML方面表示,EUV光刻设备尚未彻底准备完成,最快也要到2019年才能应用于正式生产,因此几大半导体代工厂均在DUV+多重曝光技术上继续深挖,以求撑过EUV光刻机的真空期。 7nm群英会:几大半导体代工厂部署7nm制程节点时用什么光刻技术? 三星 作为芯片代工行业的后来者,三星是“全球IBM制造技术联盟”中激进派的代表,早早就宣布了7nm时代将采用EUV。今年4月,三星刚刚宣布已经完成了7nm新工艺的研发,并成功试产了7nm EUV晶元,比原进度提早了半年。 据日本PC WATCH网站上后藤弘茂的分析,三星7nm EUV的特征尺寸为44nm*36nm(Gate Pitch*Metal Pitch),仅为10nm DUV工艺的一半左右。 除了一步到位的7nm EUV外,三星还规划了一种8nm制程。这个制程实际上是使用DUV光刻+多重曝光生产的7nm制程,继承所有10nm工艺上的技术和特性。 由于DUV光刻的分辨率较差,因而芯片的电气性能不如使用7nm EUV,所以三星为其商业命名为8nm。从这一点来看,8nm相比现有的10nm,很可能在晶体管密度、性能、功耗等方面做出了终极的优化,基本上可看做深紫外光刻下的技术极限了。 DUV和EUV光刻分辨率对比 此外,三星在7nm EUV之后,还规划了使用第二代EUV光刻技术的6nm制程,它和8nm同样是商业命名,属于7nm EUV制程的加强版,电气性能会更好。 根据三星的路线,三星将于今年下半年试产7nm EUV晶元,大规模投产时间为2019年秋季。8nm制程大约在2019年第一季度登场,而6nm制程应该会在2020年后出现。 台积电 相比三星直接引入EUV光刻的激进,台积电在7nm上选择了求稳路线,并没有急于进入极紫外光刻时代。台积电表示将继续使用DUV光刻,利用沉浸式光刻和多重曝光等技术平滑进入7nm时代,然后再转换到EUV光刻。 台积电使用DUV光刻的第一代7nm FinFET已经在2017年第二季度进入试产阶段。与目前的10nm FinFET制程相比,7nm FinFET将可在晶体管数量的情况下使芯片尺寸37%,或在电路复杂度相同的情况下降低40%的功耗。 在接下来的第二代7nm FinFET+制程上,台积电将开始使用EUV光刻。针对EUV优化的布线密度可带来约10~20%的面积减少,或在电路复杂度相同的情况下,相比7nm FinFET再降低10%的功耗。 而根据后藤弘茂的分析,台积电7nm DUV的特征尺寸介于台积电10nm FinFET和三星7nm EUV之间,Metal Pitch特征尺寸40nm,Gate Pitch特征尺寸尚不明确,但必定小于10nm时的66nm。 此外,与完全使用DUV工具制造的芯片相比,使用EUV光刻生产芯片的周期也将缩短,台积电计划在2018年第二季度开始试产7nm FinFET+晶元。 GLOBALFOUNDRIES GF此前曾是AMD自家的半导体工厂,后由于AMD资金问题而拆分独立。GF同样属于IBM“全球IBM制造技术联盟”的一员,其半导体工艺和三星同宗同源。然而GF在28nm、14nm两个节点上都遇到了重大技术难题,不得不向“后来者”三星购买生产技术。 介于此,GF在14nm之后决定放弃10nm节点,直接向7nm制程进军。虽然这个决策稍显激进,但GF也明白步子大了容易扯到啥的道理,决定在光刻技术上稳中求进,使用现有的DUV光刻技术实现第一代7nm工艺的制造,随后再使用EUV光刻进行两次升级迭代。 据其在阿尔伯尼纽约州立大学理工学院负责评估多重光刻技术的George Gomba以及其他IBM的同事透露,GF将在第一代7nm DUV产品上,使用四重光刻法。 不过在EUV的部署上,GF尚存在一些阻碍。据了解,目前ASML提供的保护膜仅适用于每小时85个晶片的生产率(WpH),而GF今年的计划是达到125WpH,这意味着现有的保护膜无法应对量产所需的强大光源。 目前,GF尚未透露将于何时开始使用EUV光刻,只说要等到“准备就绪”以后,不过看起来难以在2018年以前准备就绪。因此业界普遍猜测GF最早也要到2019年才能使用EUV光刻生产芯片。 Intel Intel作为全球最大的半导体企业,在半导体工艺方面一直保持着领先地位,并且引领了大量全新技术的发展。不过近几年,Intel半导体工艺的发展速度似乎逐渐慢了下来,比如14nm工艺竟然用了三代,10nm工艺也被竞争对手抢先。 实际上,三星和台积电在进入16/14nm节点后,在制程上常使用一些商业命名,比如上面提到的三星7nm制程,优化一下就变成了6nm。而Intel的14nm制程虽然历经两次优化,却只是以14nm、14nm+和14nm++来命名,二者已经不存在直接的可比性。 由于晶体管制造的复杂性,每代晶体管工艺中有面向不同用途的制造技术版本,不同厂商的代次之间统计算法也完全不同,单纯用代次来对比是不准确的。目前业内常用晶体管密度来衡量制程水平,实际上,Intel最新10nm制程的晶体管密度甚至反而要比三星、台积电的7nm制程更高。 而根据后藤弘茂的分析,如果将Intel、台积电、三星和GF近些年制程的特征尺寸放在一起对比,也可以看出Intel的14nm制程确实要优于三星和GF的14nm LPP以及台积电的16nm FinFET,仅略输于三星早期的10nm制程。 Intel的10nm制程则更是全面胜过台积电和三星的10nm制程,甚至比台积电和GF的第一批7nm DUV都要更好。虽然不如三星和GF的第二批7nm EUV制程,但Intel肯定也会深挖10nm制程,第二代10nm赶超三星和GF的7nm EUV也不是不可能。 关于ASML 总部位于荷兰的ASML脱胎于飞利浦,于1984年成立,至今所经营的产品主要还是光刻机。ASML凭借自己多年在行业中所积累的技术和经验,在2017年取得的收入又创出新高,净利润也同步大增。ASML的收入大致分为两个部分,一个是通过向客户供应极紫外EUV、深紫外DUV光刻机等设备获得的收入(在ASML当年的营收中占比达七成左右),另一个就是为客户提供设备安装、系统升级等服务获得的收入(在ASML当年的营收中占比约三成)。 2017年全球光刻机市场占比7成,是绝对的一哥,后面跟着的是佳能、尼康和上海微电子。 集成电路在制作过程中经历材料制备、掩膜、光刻、刻蚀、清洗、掺杂、机械研磨等多个工序,其中以光刻工序最为关键,它是整个集成电路产业制造工艺先进程度的重要指标,即在芯片制造过程中的掩膜图形到硅衬底图形之间的转移,在硅片上刻出晶体管器件的结构和晶体管之间的连接通路。 光刻机原理是把高精密底片底版投射到晶原片上,光刻机难在OVERLAY套刻精度以及产率。需要精密的光学镜头,和精密的对焦稳定,和散射极低的光源激光。镜头虚,有云翳,不行,对焦丝扣不匀不细,不稳,不行。光源散射也不行。要比千分尺(螺旋测微器)更细更稳。 用螺旋测微器原理,精密螺纹调焦对焦,稳定相距焦平面。工作台的膨胀,减震,连续工作的精准,都对精度要求极高。小试验室小作坊,做一两个己经很难,大批量生产,精度就更难。 其实这些年来,国内早就有设备厂商,以及研究机构在对光刻机进行研发。如上海微电子、中电科四十五所、中电科四十八所等,但是离国外几家光刻机厂商差距甚远,更别提在先进节点上的顶尖光刻设备差距了。
  • 2013-7-19 18:20
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    As has been the case for the past several years, apprehension over the development of extreme ultraviolet (EUV) lithography was one of the oft-repeated themes at this year's Semicon West fab tool tradeshow in San Francisco, United States. "EUV is the highest priority for our industry," said Luc Van den Hove, president and CEO of European microelectronics research institute Imec, in a panel discussion at the event. In May, Dutch lithography vendor ASML finalized a deal to acquire lithography source vendor Cymer for about $2.6 billion. The deal is largely considered an attempt by ASML to take a firmer hand in the development of an EUV source. Cymer is one of three developers trying to create a source that would be powerful enough to support commercial production throughput of an EUV lithography tool. In February, at the SPIE Advanced Lithography Conference, ASML showed data indicating that it had raised the maximum power on its power source to 55 watts. Ryan Young, a spokesman for ASML, said this week that 55 watts would be enough to support EUV tool throughput of about 43 wafers per hour. More significant, according to Young, is that ASML has shown the power source can support a maximum power of 50 watts for long periods of time. Young also noted that the development work is being done on ASML's pre-production EUV machine, the NXE:3100. When ASML transfers the source to its NXE:3300 EUV tool, which has a larger drive laser, the 50 watts will become 80 watts, enough to support throughput of more than 60 wafers per hour. Young added that improving source power—while the most significant stumbling block to putting EUV in production—is only one place where ASML needs to make progress. ASML will continue working on improving the raw power of the source, but also focus on other needed improvements in the power source around availability and dose control. ASML's latest goal is to be able to support a throughput of about 70 wafers per hour sometime in 2014. According to Young, that's roughly the throughput threshold that most customers say would make it worthwhile to adopt EUV. "But every customer's process is different," he added. Chipmakers would ideally prefer EUV tools with a throughput of 100 to 150 wafers per hour to make production cost effective. Some say a tool throughput of 60 to 80 wafers per hour would be a sufficient starting point. The original plan was for EUV to be in production years ago, but development hiccups have pushed out the technology multiple times. ASML has six pre-production EUV development tools currently in the field. Intel—which last year acquired a 15 per cent stake in ASML and ponied up additional funds specifically for the development of EUV in a deal worth a total of $4.1 billion—has been hoping to deploy EUV lithography at the 10 nm node in the second half of 2015. Intel also said it would be prepared to extend optical immersion lithography to that node in the event that EUV is not ready. Samsung and TSMC have entered into similar deals with ASML. Ludo Deferm, executive vice president of business development at Imec, said this week that extending optical immersion to that node may not be economically feasible. Because extending optical immersion to 10 nm could require three or more exposures—and thus three or more photomasks for critical layers—the costs involved would increase exponentially. But Deferm told us Imec is confident that EUV will eventually be put in production. "We are confident that it will come," he said. "I don't have a crystal ball, either. We can't predict the future."   Dylan McGrath EE Times  
  • 2012-7-28 13:01
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    Proponents of extreme ultraviolet (EUV) lithography were reasonably encouraged a few weeks ago when Intel Corp. entered into a $4.1 billion equity and funding deal to help boost RD efforts for 450-mm and EUV lithography tools . "It's the best news I've heard in a long time," said David Brandt, senior director of euv marketing and business development at Cymer Inc., a long-time source developer for ASML and the front-runner in working with the Dutch lithography vendor to improve source power for EUV tools. Intel already had a vested stake in making sure that EUV development remains on track to put the technology into production, even if much later than Intel had originally hoped. Intel and the rest of the thinning ranks of leading-edge chip makers have every reason to want cost-effective EUV lithography to save them from the pain and expense of extending 193-nm optical lithography to the 10-nm node and beyond. Brandt and others took Intel's willingness to put skin in the EUV game as a vote of confidence in the viability of the oft-delayed technology. But Intel's wallet alone won't bring EUV into production. Though incremental progress on the EUV development front has been reported over the past week, there remains—as there has since the technology landed on the ITRS roadmap—work to be done. EUV is, at best, still years away from volume production and remains no slam dunk. In a presentation at last week's Semicon West tradeshow, Franklin Kalk, chief technology officer at Toppan Photomasks Inc., said source power, mask defectivity and photoresist performance remain the three issues still facing volume production of chips using EUV. But, Kalk said, source power remains the main hurdle, as it has for some time. Three years ago, Kalk said, mask defectivity was considered the main stumbling block for EUV, and thus the burden of Toppan and its competitors. But in the past couple of years, the failure to develop a source powerful and reliable enough to provide adequate tool throughput has taken centre stage. "I'm hoping that source power gets high enough that they start complaining about the masks again." Chip makers want EUV tools with a throughput of 100 to 150 wafers per hour to make production EUV cost effective. Some say a tool throughput of 60 to 80 wafers per hour would be a sufficient starting point. Even that type of throughput remains out of reach for now, though AMSL CEO Eric Meurice said this week that research progress indicates that EUV throughput is on pace to reach 70 wafers per hour in 2014 and 125 wafers per hour in 2016. More incremental progress Other EUV progress has also been reported in the previous weeks: On source power: Nigel Farrar, vice president of technical marketing at Cymer, said Cymer has now achieved about 50 watt expose power on its HVM I source using a pre-pulse—which conditions the target prior to the main pulse—at full repetition rate using closed loop controls. (Back in February, Cymer also reported average power of 50 watts, but that was in open loop testing, minus the power-reducing controls placed on systems in the field to improve stability.) Meurice said the potential for 105 watts has been confirmed in lab experiments, supporting ASML's roadmap to volume production starting at 70 wafers per hour in 2014 and upgradable to 125 wafers per hour in 2016. He cautioned that in-situ experiments, as opposed to lab experiments, are still necessary to confirm this roadmap. Even if ASML stopped development now, Meurice said the lab data demonstrated that ASML's NXE:3300—the production tool successor to the pre-production NXE 3100 systems installed at several customer sites—would support throughput of 30 to 40 wafers per hour based on its superior architecture and energy efficiency. (Halting development, of course, is not the plan). Source availability: Farrar said Cymer's HVM I sources have been running at about 70 per cent availability for the past two quarters, up from 50 per cent in prior quarters. Only about 10 per cent of the downtime was unscheduled, the rest was for planned maintenance. Source collector durability: Cymer has demonstrated stable reflectivity for its EUV source collector over more than 30 billion pulses. Collector reflectivity is a key issue because replacing the collector is a major undertaking and the collector's performance will degrade over time. Cymer does not know how long the source can last between replacements, but 30 billion pulses over more than a year is considered encouraging. Mask defectivity: Kalk acknowledged that EUV masks will not be defect-free. Due to the complexity involved, every EUV mask blank will have defects, an multi-layer mask blank defects cannot be repaired, Kalk said. But masks must be "defect free enough" to work, he said. In the case of memory, design patterns are redundant enough that the mask can be shifted and rotated accordingly in order to write the pattern around the defects—if mask makers know where they are, according to Kalk. Improvement in both blank and mask inspection tools, as well as mask writer accuracy, is required, Kalk said. Mask durability: No one will know exactly how long an EUV mask will last until they are used in high volume production. Kalk said different mask durability issues—including the appearance of haze on a mask and, later, mask absorber degratdation—arose in the first six years or so after the introduction of 193-nm lithography, depending on the number of exposures for a mask. "We are going to encounter issues," Kalk said. 'I don't even know what they are yet, but we are going to encounter them." Tools needed: The full tool kit for EUV masks won't be ready until about 2018, according to Kalk. He said development is needed on blank and mask inspection tools, as well as the Carl Zeiss EUV actinic aerial image metrology system (AIMS) for reticle defect and printability analysis. Kalk said that EUV insertion can occur before the full mask tool kit is in place, but that a "bridge strategy" will be required. As manufacturing eventually ramps up, new issues will arise he said.  
  • 2012-7-20 09:01
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    电子发烧友网讯: 光刻设备厂商ASML Holding NV的CEO Eric Meurice 宣称该公司已经投入到下一代元紫外线光刻技术(EUV)设备的研发中,同时保证其生产能力能够达到客户的需求。   大部分厂家认为EUV光刻是实现微型化电路的必备技术,这项技术已经研发了差不多十年,但目前仍然被其低功率光源困扰。   Meurice在一个讨论公司第二季度的财报的财务分析的会议上提到,他们会提供更多EUV的信息,以便公司更深入了解其将推出的商用EUV设备NXE:300。这是头11部相关工艺开发的设备,能够处理300mm直径的晶圆。   但短期内ASML对生产能力进行太多的承诺,Meurice声称到年底的时候,每个小时加工的晶圆或许只有70片,但目前已经有规划,到2014年每小时的盛长亮可以达到70片,而到2016,这个数字会上升到125。当客户需要450mm的加工设备时,可以增加10%的价格,从而由ASML获得相对应的产品,Meurice强调。   Meurice继续说到ASML总共有11台NXE:3300提供订购,但目前来说这些设备在2013年前都未能够交付给客户。他继续说到首台设备会在十月或十一月在ASML组装完成。   2013年推出的 NXE:3300系统只能用来发展制作工艺技术,但给ASML在当年带来大概8亿欧元的收益。   Meurice说道,为EUV所寻找的适合光源已经在鉴定一段时间了,同时供应商已经多次证明50瓦特光源和概念上是105瓦特的光源已经在实验室试验中得到确认。他继续强调,到2014年这些会给平台带来每小时70片晶圆的产能,而两年后这个数字就会上升到125。   NXE:3300在原地的实验必须确认这点,同时Meurice声称公司到下一个夏天会确认这些发展路线。   这种发展的观点使我们得到了顾客的认可,从而购买了四台额外的NEE:3300系统,这样的话,总共就有15台设备在准备,到2014年,它们将会是首批能够工作在EUV的半导体设备。   ASML的高管继续确认额外的四台NXE:3300设备是被一家DRAM厂家预定,同时他们正在和另外的DRAM厂家洽谈,以卖出更多的设备,这些都会在2014年交付。与此同时,他们正与一个逻辑方面的公司洽谈更多的设备提供,这估计会在2015年移交。Meurice声称,他们正在筹划14/12/11nm节点的产品,因为无论在任何地方,14/12/11mm的产品都会被当做同一类型的工艺。   当被问到NEX:3300的最初产能是多少的时候,Meurice解析道头11部机器并没有行相关的规定。但以后的设备会有一个固定的限制,   我们能看到的最小差能是每小时30片,如果我们在第一步机器面前碰到问题,例如耗费更多工作去稳固控制机构,这通常会花费两三个月甚至半年的时间,这样的话我们怎么去要求生产能力从30片每小时发展到70。 电子发烧友网讯: 光刻设备厂商ASML Holding NV的CEO Eric Meurice 宣称该公司已经投入到下一代元紫外线光刻技术(EUV)设备的研发中,同时保证其生产能力能够达到客户的需求。   大部分厂家认为EUV光刻是实现微型化电路的必备技术,这项技术已经研发了差不多十年,但目前仍然被其低功率光源困扰。   Meurice在一个讨论公司第二季度的财报的财务分析的会议上提到,他们会提供更多EUV的信息,以便公司更深入了解其将推出的商用EUV设备NXE:300。这是头11部相关工艺开发的设备,能够处理300mm直径的晶圆。   但短期内ASML对生产能力进行太多的承诺,Meurice声称到年底的时候,每个小时加工的晶圆或许只有70片,但目前已经有规划,到2014年每小时的盛长亮可以达到70片,而到2016,这个数字会上升到125。当客户需要450mm的加工设备时,可以增加10%的价格,从而由ASML获得相对应的产品,Meurice强调。   Meurice继续说到ASML总共有11台NXE:3300提供订购,但目前来说这些设备在2013年前都未能够交付给客户。他继续说到首台设备会在十月或十一月在ASML组装完成。   2013年推出的 NXE:3300系统只能用来发展制作工艺技术,但给ASML在当年带来大概8亿欧元的收益。   Meurice说道,为EUV所寻找的适合光源已经在鉴定一段时间了,同时供应商已经多次证明50瓦特光源和概念上是105瓦特的光源已经在实验室试验中得到确认。他继续强调,到2014年这些会给平台带来每小时70片晶圆的产能,而两年后这个数字就会上升到125。   NXE:3300在原地的实验必须确认这点,同时Meurice声称公司到下一个夏天会确认这些发展路线。   这种发展的观点使我们得到了顾客的认可,从而购买了四台额外的NEE:3300系统,这样的话,总共就有15台设备在准备,到2014年,它们将会是首批能够工作在EUV的半导体设备。   ASML的高管继续确认额外的四台NXE:3300设备是被一家DRAM厂家预定,同时他们正在和另外的DRAM厂家洽谈,以卖出更多的设备,这些都会在2014年交付。与此同时,他们正与一个逻辑方面的公司洽谈更多的设备提供,这估计会在2015年移交。Meurice声称,他们正在筹划14/12/11nm节点的产品,因为无论在任何地方,14/12/11mm的产品都会被当做同一类型的工艺。   当被问到NEX:3300的最初产能是多少的时候,Meurice解析道头11部机器并没有行相关的规定。但以后的设备会有一个固定的限制,   我们能看到的最小差能是每小时30片,如果我们在第一步机器面前碰到问题,例如耗费更多工作去稳固控制机构,这通常会花费两三个月甚至半年的时间,这样的话我们怎么去要求生产能力从30片每小时发展到70。     光刻设备厂商ASML Holding NV的CEO Eric Meurice 宣称该公司已经投入到下一代元紫外线光刻技术(EUV)设备的研发中,同时保证其生产能力能够达到客户的需求。   大部分厂家认为EUV光刻是实现微型化电路的必备技术,这项技术已经研发了差不多十年,但目前仍然被其低功率光源困扰。   Meurice在一个讨论公司第二季度的财报的财务分析的会议上提到,他们会提供更多EUV的信息,以便公司更深入了解其将推出的商用EUV设备NXE:300。这是头11部相关工艺开发的设备,能够处理300mm直径的晶圆。   但短期内ASML对生产能力进行太多的承诺,Meurice声称到年底的时候,每个小时加工的晶圆或许只有70片,但目前已经有规划,到2014年每小时的盛长亮可以达到70片,而到2016,这个数字会上升到125。当客户需要450mm的加工设备时,可以增加10%的价格,从而由ASML获得相对应的产品,Meurice强调。   Meurice继续说到ASML总共有11台NXE:3300提供订购,但目前来说这些设备在2013年前都未能够交付给客户。他继续说到首台设备会在十月或十一月在ASML组装完成。   2013年推出的 NXE:3300系统只能用来发展制作工艺技术,但给ASML在当年带来大概8亿欧元的收益。   Meurice说道,为EUV所寻找的适合光源已经在鉴定一段时间了,同时供应商已经多次证明50瓦特光源和概念上是105瓦特的光源已经在实验室试验中得到确认。他继续强调,到2014年这些会给平台带来每小时70片晶圆的产能,而两年后这个数字就会上升到125。   NXE:3300在原地的实验必须确认这点,同时Meurice声称公司到下一个夏天会确认这些发展路线。   这种发展的观点使我们得到了顾客的认可,从而购买了四台额外的NEE:3300系统,这样的话,总共就有15台设备在准备,到2014年,它们将会是首批能够工作在EUV的半导体设备。   ASML的高管继续确认额外的四台NXE:3300设备是被一家DRAM厂家预定,同时他们正在和另外的DRAM厂家洽谈,以卖出更多的设备,这些都会在2014年交付。与此同时,他们正与一个逻辑方面的公司洽谈更多的设备提供,这估计会在2015年移交。Meurice声称,他们正在筹划14/12/11nm节点的产品,因为无论在任何地方,14/12/11mm的产品都会被当做同一类型的工艺。   当被问到NEX:3300的最初产能是多少的时候,Meurice解析道头11部机器并没有行相关的规定。但以后的设备会有一个固定的限制,   我们能看到的最小差能是每小时30片,如果我们在第一步机器面前碰到问题,例如耗费更多工作去稳固控制机构,这通常会花费两三个月甚至半年的时间,这样的话我们怎么去要求生产能力从30片每小时发展到70。
  • 热度 1
    2012-7-17 12:18
    1118 次阅读|
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    When the semiconductor industry began the migrated from 200-mm wafers to 300-mm wafers more than a decade ago, chip makers convinced tool suppliers to foot the bill for the RD required to make the move with the promise that they would be justly and richly rewarded with robust sales of the new systems, which much of the industry appeared anxious to adopt. But they were left holding the bag when the dot come bubble burst and—surprise—chip makers decided to delay deployment of 300-mm capacity. Many equipment industry executives were understandably bitter about this. This was in large part the reason that, when chip makers first began making noise about moving to 450-mm wafers a few years ago, the sound you heard was mostly echos and crickets chirping. A lot of people were skeptical right from the beginning that 450-mm would happen at all. Now it appears that 450-mm is inevitable, though the conventional wisdom holds that only a handful of chip makers—notably Intel Corp., Samsung Electronics Co. Ltd., Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and Globalfoundries Inc.—will ever build 450-mm manufacturing lines. Still, right from the start, there has been much debate about how tool suppliers and their customers would divvy up the RD costs associated with moving to the new wafer size. (Bob Johnson of Gartner Inc. said this week that the cumulative cost of 450-mm development will be about $17 billion, about $2 billion of which is being spent this year, though he acknowledged that other estimates vary widely). Some fledgling development efforts are now well underway, including the Global 450 Consortium, a $4.8 billion collaborative effort housed at the Albany NanoTech Complex and backed by the companies mentioned above, as well as IBM Corp. For some tool makers, though, this was not enough. ASML Holding NV, the dominant player in lithography equipment, was largely seen dragging its feet on 450-mm. Moving to 450-mm will require new lithography equipment with more advanced stages that can support the increased size and weight without creating vibrations that would make accurate lithography exposure impossible. Given the fact that no more than a handful of chip makers are expected to buy the new tools, ASML foresaw a limited return on the considerable investment that would be required. ASML of course has now come around, but only after the firm devised an innovative equity-plus-research funding scheme that asks those chip makers with the most to gain from the move to 450-mm wafers—and extreme ultraviolet (EUV) lithography that matter—to foot some of the bill for new technology up front. Last week, Intel announced it would acquire a 15 percent stake in ASML as part of a $4.1 billion deal to accelerate the development of 450-mm and EUV lithography. In addition to paying over $3 billion for the stake in ASML, Intel is also contributing more than $1 billion more directly to the development of the new technologies. Intel, of course, also committed to advanced purchase orders for 450-mm and EUV development and production tools. Samsung, TSMC must pony up ASML is willing to sell another 10 percent of the company to other chip makers who are willing to kick in for the development of 450-mm litho tools and EUV. The firm is currently in discussions with both Samsung and TSMC on taking a piece of the action. If those firms decline to participate, or agree to participate but don't collectively buy the entire 10 percent remaining that ASML is willing to sell, ASML will invite others to participate. (As a condition imposed by ASML, Intel's stake in the company is limited to a maximum of 15 percent.) The whole thing is not unlike a waiter bringing the check before serving the meal. But it had to be this way. ASML was not going to put out the investment required on 450-mm without money up front. And owing to its dominant market share in leading-edge lithography tools, there will be no 450-mm chip production without ASML. Intel has the most to gain from the move to 450-mm. Stacy Smith, the company's chief financial officer, said this week that it expects the move to 450-mm to save the company more than $10 billion in manufacturing costs. Still, Intel alone takes ASML up on its offer, its deep pockets will no doubt also benefit rivals who will then get access to 450-mm and EUV lithography tools. That's where the 15 percent stake comes in. Even if Intel is the only chip firm to directly support ASML's development of these technologies, the world's biggest chip maker will get a piece of the action every time a rival pulls out its checkbook to buy one of the new tools. In the words of a spokesman for ASML, Intel now has real skin in the game and even more interest in seeing the development of these technologies succeed. Whether Samsung, TSMC or any other chip vendor takes ASML up on its offer remains to be seen. On one hand, it can be argued, there is little incentive for them to do so at this point. Especially now that Intel has put its money where its mouth is, there is little doubt that ASML will develop 450-mm tools (though for EUV, the case is far from closed). Once ASML has the tools available, they will presumably be happy to sell them to Samsung, TSMC and anyone else who wants them and has the means to pay. But Samsung and TSMC would be wise to pony up and get involved. When 450-mm tools become available, the leading-edge chip makers will want them ASAP. While there is no publicly disclosed intent to give Intel right of first refusal on new tools—other than those Intel has already committed to buying—come sense dictates that you take care of any part owners of your company before shopping them to the general public. If Samsung and TSMC don't get in on the ground floor (first floor?), they may end up waiting until Intel is pretty sure it has all of the tools it wants before they get their hands on any. Also, Intel's 15 percent stake in ASML—as well as any stake Samsung and TSMC may take—is in non-voting shares. But again, common sense dictates that the customer who is helping to foot the bill for the development of the technology will have a louder voice when it's time to make development decisions. Samsung, TSMC and any other firm that does not get in on the action may find itself outside looking in.  
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